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Unique identifier: 73ac5764-3d25-42b6-a63c-bd82acf41d37

1. Descrição do cargo/posição/bolsa
1. Job description

Job:
One research grant(s) Bolsa de Investigac¸a~o - Mestre is now available in project SARRROCA, “Synthetic Aperture Radar Robust Reconfigurable Optimized Computing Architecture” - ref: PTDC/EEI-HAC/31819/2017 funded by FCT/MCTES through national funds, and, where appropriate, POCI - Programa Operacional Competitividade e Internacionalização e PORLisboa – Programa Operacional Regional de Lisboa

Job/Fellowship Reference: One research grant(s) Bolsa de Investigac¸a~o - Mestre is now available in project SARRROCA, “Synthetic Aperture Radar Robust Reconfigurable Optimized Computing Architecture” - ref: PTDC/EEI-HAC/31819/2017 funded by FCT/MCTES through national funds, and, where appropriate, POCI - Programa Operacional Competitividade e Internacionalização e PORLisboa – Programa Operacional Regional de Lisboa

Main research field: Engineering

Sub research field:

Job summary:

This research work aims to develop a fault-tolerant embedded system. The research work will involve designing novel hardware architectures and study and implementation of adequate fault-tolerant mechanisms. Expected outputs of this work are the implementation of prototypes for real-time fault-tolerant architectures.



Job description:

Research Grant

(Bolsa de Investigac¸a~o - Mestre)

(SARRROCA, “Synthetic Aperture Radar Robust Reconfigurable Optimized Computing Architecture” - ref: PTDC/EEI-HAC/31819/2017)

35_2019_31819_BM

The Instituto de Engenharia de Sistemas e Computadores, Investigação e Desenvolvimento em Lisboa (INESC-ID) Portugal is one of the largest and most dynamic research institutes in Portugal in the areas of Computing Systems and Communication Networks, Embedded Electronic Systems, Information and Decision Support Systems, Interactive Intelligent Systems and Energy Systems.

One research grant(s)  Bolsa de Investigac¸a~o - Mestre is now available in project SARRROCA, “Synthetic Aperture Radar Robust Reconfigurable Optimized Computing Architecture” - ref: PTDC/EEI-HAC/31819/2017 funded by FCT/MCTES through national funds, and, where appropriate, POCI - Programa Operacional Competitividade e Internacionalização e PORLisboa – Programa Operacional Regional de Lisboa, under the following conditions:

Duration

Six months from 1 of October 2019. The grant may be renewed within the period of the project, not exceeding the maximum period set by FCT for such grants. Renewal is subject to suitable performance

Legislation

A fellowship contract will be celebrated according to the Regulations for Research Grants of the Foundation for Science and Technology in force the INESC ID Grant regulations approved by FCT, and to the Status of Scientific Research Fellow (Lei nº 40/2004 de 18 de Agosto, and its successive amendments).

Monthly amount

The monthly amount of the grant 989,70 is in accordance with the values stipulated in the “Regulations for Research Grants of the Foundation for Science and Technology” in force (https://www.fct.pt/apoios/bolsas/regulamentos.phtml.pt) and (http://www.fct.pt/apoios/bolsas/valores) and INESC-ID Lisboa Grant Regulations approved by FCT, and shall be rendered through a monthly bank transfer to an account held by the grantee

Objectives / summary

This research work aims to develop a fault-tolerant embedded system. The research work will involve designing novel hardware architectures and study and implementation of adequate fault-tolerant mechanisms. Expected outputs of this work are the implementation of prototypes for real-time fault-tolerant architectures.

Scientific supervision

The activity will be supervised by Rui Duarte, researcher at INESC-ID Lisboa. The grantee will be integrated at INESC-ID in the Electronic System Design and Automation (ESDA) group, https://www.inesc-id.pt/action-line/EES/.

 

Required education Level and research experience

The candidate should have an MSc degree in Computer Science and Engineering, or Electrical and Electronic Engineering and research project experience in System on a Chip design using FPGAs from Xilinx.  The candidate should be familiarized with most common fault-tolerance mechanisms on FPGAs. Language skills - proficiency in English.

Evaluation criteria

Academic record of the candidate and interest for the following areas of research academic record (25%), experience with Xilinx FPGAs (25%). The Jury will interview the two candidates with higher classification.  In order to perform a more objective evaluation of some of the criteria, the interview will count for 50% of the evaluation of each criteria above."

The jury will convene in 30 September 2019 and is composed of

Name

Professional Status / Institution

Rui Duarte

researcher / Inesc-Id

José Teixeira de Sousa

Assistant Professor / IST-DEEC

Horácio Neto

Associate Professor / IST-DEEC

Results

The final evaluation results will be publicized through an ordered list, and the candidates will be notified of the Jury decision by email.

Formalisation of applications

Applications are formalised by sending an email to rpd@inesc-id.pt with the documents stated bellow.  The application email should clearly state the reference of the project.

detailed curriculum vitae

motivation letter

single copy of official academic degree certificate with detailed list of grades, required in education level.

name of two personal references

*For candidates with degrees granted by foreign higher education institutions it is mandatory to have a degree or diploma recognition.  For more information press here.

 

Application Dates

 

From

 

To

 

28 August 2019

 

28 September 2019

 




Vacant posts: 1

Type of contract: Information not available

Job country: Portugal

Job city: Lisboa

Job company/institute: inesc id


Application deadline: 28 Setembro 2019
(The Application's deadline must be confirmed on the Job Description)

2. Dados de contactos da organização
2. Organization contact data

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3. Habilitações académicas
3. Required education Level


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4. Línguas exigidas
4. Required languages


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5. Experiência exigida em investigação
5. Required research experience


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